Embedded

What’s involved in simulation of a complex SoC FPGA like Versal ACAP?

AMD’s Versal adaptive compute acceleration platform (ACAP) is a system-on-chip (SoC) device architecture (see figure 1) includes three groups of engines – scalar, adaptable, and intelligent – plus ...
Yahoo Finance

MicroCloud Hologram Inc. Launches FPGA-Based High-Performance Surface Code Quantum Simulation Platform

SHENZHEN, China, April 15, 2026 (GLOBE NEWSWIRE)-- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, launched a simulator that fully leverages the ...
Yahoo Finance

MicroCloud Hologram Inc. FPGA-Based High-Performance Surface Code Quantum Simulation Platform: Efficient Error Correction Algorithm Validation under Rotated Layout

SHENZHEN, China, Feb. 25, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, has developed a surface code quantum simulator based ...
Seeking Alpha

MicroCloud Hologram Inc. Builds the Industry's First Multi-FPGA Quantum Fourier Transform Simulation Solution

SHENZHEN, China, Jan. 8, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, launched a brand-new scalable quantum Fourier transform ...
EDN

ASIC, FPGA simulator reduces run times

The Riviera 2005.08 ASIC, FPGA simulator tool provides VHDL and Verilog Linting and support for 64-bit Linux operating systems. The tool features a redesigned simulation engine that reduces simulation ...
Seeking Alpha

MicroCloud Hologram Inc. Develops Serial-Parallel Architecture-Based FPGA Quantum Computing Simulation Framework

SHENZHEN, China, Dec. 22, 2025 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (HOLO), (“HOLO” or the "Company"), a technology service provider, launched a brand-new FPGA-based quantum computing ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and Verification

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...
Electronic Design

Mixed-Language Simulator Serves FPGA Designers

In the Active-HDL Designer Edition, a low-cost mixed-language RTL simulator, designers gain a high-performance simulator for designs targeted at FPGAs. Basically, FPGA designers have been forced to ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...